(1) Field of the Invention
The present invention relates generally to an apparatus for converting analog-to-digital or digital-to-analog signals, and more particularly to a robust sigma-delta modulator for implementing a high-precision analog-to-digital or digital-to-analog converter.
(2) Description of the Prior Art
Sigma-delta modulators have become a popular means to implement high-precision analog-to-digital converters (ADC's) or digital-to-analog converters (DAC's) in that the technique enables the realization of high-resolution data converters while requiring only low to moderate precision analog components. FIG. 1 shows a detailed block diagram of a conventional sigma-delta modulator 10. Modulator 10 consists of a summing junction 12, a filter circuit 14, a quantizer 16 and a DAC 18 within a feedback circuit. Sampling switch 20 provides analog input X(z) to summing junction 12 at the frequency of sampling clock 22. The output 24 of summing junction 12 is provided to filter circuit 14 with the output 26 of filter circuit 14 provided to quantizer 16. Quantizer 16 is also controlled by sampling clock 22 to convert the analog signal produced by filter circuit 14 to an output pulse density modulated (PDM) digital signal Y(z). The output Y(z) is also fed back to DAC 18, which reconverts the digital signal to an analog signal 28. Signal 28 is then applied to the negative input of summing junction 12, such that, unless the output Y(z) is exactly the same as input X(z), an error signal will be developed by summing junction 12 which will then pass through the loop to correct the output. This feedback loop filters the difference between the previous output and the current input sample. By means of algebraic decomposition and linearity assumptions of quantizer 16, input signal X(z) is passed through a low pass filter that is wider than the desired band, while the quantization error, i.e., the difference between the value input to quantizer 16 and the value output from quantizer 16, is filtered by a high pass filter with good stop band suppression. Hence the signal is passed unsuppressed while the quantization noise is attenuated in the band of interest. Consequently, these devices have a relatively low conversion rate when compared to other ADC's and DAC's due to the necessary high OSR. Apart from limiting the frequency range, high OSR's negatively impact power dissipation and the settling requirements for the amplifiers employed in the discrete-time analog integrators. It is therefor of great practical interest to find alternative modulator topologies that can cope with low OSR's while preserving the inherent insensitivity of the converter with regard to its constituent analog components.
Three basic ways of reducing the OSR are known in the art. The first method is to replace the typical single-bit quantizer at the modulator output by a multi-bit quantizer as described by Larson, L. E., Cataltepe, T. and Temes, G. C. in "Multi-bit Oversampled Sigma-Delta A/D Converters With Digital Correction", IEE Electronics Letters, vol. 24, pp. 1051-1052, August 1989. This method not only reduces the quantization noise thus increasing the dynamic range of the converter, but also de-correlates the quantization noise spectrum from the input signal. Such a system is less likely to fall into a cyclic behavior which can give rise to spurious tones in the passband. However, the major drawback of this method is the extremely high linearity requirement for the DAC in the feedback path of the modulator multi-loop configuration. It is noted that the required accuracy of this DAC must be greater than or equal to the quantization noise suppression in the modulator pass band. For example, if the modulator accuracy needs to be 16 bits, then the integral linearity of the DAC must be no worse than 96 dB or 0.00158%, since DAC errors are added unfiltered to the input signal, as shown in FIG. 1. Integral linearity errors in the DAC will produce unwanted tones, i.e., harmonic distortion, which will limit the system accuracy to that of the total harmonic distortion. Unfortunately, the DAC integral linearity is directly dependent upon the relative error in the ratios of values derived from monolithic passive components. Thus, since this ratio of values is 0.01% at best, the integral linearity error can be kept to no better than 0.01%. making it difficult to obtain greater than 60 dB, or 10 bit accuracy due to the harmonic distortion.
In a second approach, the single modulator loop is replaced by a multi-loop configuration whereby the additional loop(s) create an estimate of the quantization noise of the previous loop(s). The noise estimate is digitally subtracted from the previous loop output(s). The multi-loop solution whitens the quantization noise and thus prevents the occurrence of spurious tones. In theory, one can achieve arbitrarily good noise shaping by cascading a sufficient number of stages. However, the reduction of the quantization noise by signal subtraction requires well matched capacitor ratios in the analog modulator loops and extremely high op-amp open-loop gain values to minimize integrator leakage. These requirements practically limit the number of cascaded stages to two or three. Even with two or three stages, 15 to 16 bit accuracy is difficult to achieve.
In the third approach, the order of the loop filter is increased such that a more stable noise shaping filter is possible. The multiple feedbacks of a higher order system tend to de-correlate the quantization noise from the input signal. In contrast to the multi-bit solutions, high-order single-bit modulators preserve the insensitivity of single-bit low-order circuits with respect to minor variations of the analog component values. The major drawback of this approach is that there is a progressive reduction in quantization noise suppression gains as the OSR is lowered in order to maintain a stable operating point.